The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with a flip chip bonded integrated circuit.
The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Flip chip technology answers the demand for improved input/output (I/O) connections from the chip to external systems. On a flip chip, the electrical components are located (face down) on the side of the die which attaches to the chip package. In this manner, the flip chip provides a short interconnection length using, for example, ball-grid array (BGA) solder connections. The self-aligning nature of the solder bumps offers the advantages of higher density mounting, improved electrical performance and reliability, and better manufacturability. The positioning of the circuit side is the source of many advantages in the flip chip design. However, in other regards, the orientation of the die with the circuit side face down on a substrate is a disadvantage. For example, access to the circuit region is sometimes necessitated in order to modify or debug a finished chip. Additionally, access to the circuit region is often required through manufacturing stages in order to test and analyze circuit""s integrity. In this event, it is necessary to burrow through the body of the flip chip die or through the chip package in order to access the circuit region.
Various methods have been employed to quickly and effectively access the circuit region. A popular method includes milling or grinding off portions of the die, or the chip packaging in order to burrow through to the circuit region. One difficulty with this method is its accuracy. Since the circuit region is formed in a very thin epitaxial layer, with a typical thickness of only 10-20 micrometers (xcexcm), an overshoot in the milling process can grind through the very circuit for which the testing was intended. Another problem connected to milling the flip chips down is that the process yields a thinner overall structure. The xe2x80x9cthinnedxe2x80x9d die/chip package combination is structurally much weaker. In certain circuit analysis or modification processes, the flip chip die must be removably connected to multiple testing equipment. Typically, the connection between the die and the equipment is made with heat sensitive adhesives. Later, heat is used to loosen and remove the die from the testing equipment. In this process, the xe2x80x9cthinnedxe2x80x9d and structurally fragile die can curl or short circuit, in effect, rendering the silicon die unsuitable for farther analysis or use. For these reasons, it is necessary to have a method and device which will provide added support and rigidity to flip chip dies. An improved method and device should desirably accommodate multiple rounds of circuit testing and debugging.
The above mentioned problems with integrated circuit technology and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A device and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a method for accessing a circuit region on a flip chip die. The method includes mounting the flip chip die on a polishing tool. The flip chip die is attached to a chip package. At least two spacers are used to adjust the placement of the flip chip die in the polishing tool. The at least two spacers adjust the placement of the flip chip die to expose portions of the chip package to a polishing blade. The at least two spacers are polished portions taken from the chip package. The circuit of the flip chip die is accessed.
In another embodiment, a device for accessing a circuit region on a flip chip die mounted on a chip package is provided. The device includes a polishing tool. The polishing within the tool is adapted for mounting the flip chip die within the tool. A number of spacers are removably placed within the polishing tool to adjust the mounting of the flip chip die.
In another embodiment, a system for accessing a circuit region on a flip chip die that is mounted circuit side down on a ceramic package is provided. The system includes a device for accessing the circuit region on the flip chip die. The device includes a polishing tool and the polishing tool is adapted for mounting the flip chip die within the polishing tool. A number of spacers are removably placed within the polishing tool to adjust the mounting of the flip chip die. A controller electrically couples to the polishing tool for controlling the operation of the polishing tool.
Thus, a more effective and efficient method and device are provided for adding support and rigidity to flip chip dies. The method and device can facilitate multiple rounds of circuit testing and debugging. The result of the method and device is a durable casing for flip chip device analysis.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.